DESIGN
5 V → 3.3 V LDO Regulator Board (reference design)
The KiNecta acceptance project: AMS1117-3.3, 22 µF in/out, ERC-clean, DRC-clean, sim-verified.
The canonical KiNecta reference workflow in one download.
What's inside:
- ldo-regulator.kinsch — schematic, hierarchical-ready, netlist-coherent
- ldo-regulator.kinpcb — 2-layer board, 0.2 mm clearance rules, GND zone with thermal reliefs
- ldo-regulator.kinpro — project with ERC severities and net classes
Verified: ERC 0 errors · DRC PASS across all test groups · ngspice DC load sweep 0–500 mA, VOUT 3.297–3.301 V (assert range [3.23, 3.37] V).
Use it to test your toolchain, as a template, or to learn the file formats.
What's inside:
- ldo-regulator.kinsch — schematic, hierarchical-ready, netlist-coherent
- ldo-regulator.kinpcb — 2-layer board, 0.2 mm clearance rules, GND zone with thermal reliefs
- ldo-regulator.kinpro — project with ERC severities and net classes
Verified: ERC 0 errors · DRC PASS across all test groups · ngspice DC load sweep 0–500 mA, VOUT 3.297–3.301 V (assert range [3.23, 3.37] V).
Use it to test your toolchain, as a template, or to learn the file formats.